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(parent: 8b7e6b0) | patch
target/ppc: Add POWER10 exception model
authorNicholas Piggin <npiggin@gmail.com>
Sat, 1 May 2021 07:24:35 +0000 (17:24 +1000)
committerDavid Gibson <david@gibson.dropbear.id.au>
Tue, 4 May 2021 03:12:46 +0000 (13:12 +1000)
commit526cdce771fa27c37b68fd235ff9f1caa0bdd563
tree17ecd66691cbeb0e317e767001362a637200a3d0tree | snapshot
parent8b7e6b07a46809a75b857d30ae47e697e0f9b724commit | diff
target/ppc: Add POWER10 exception model

POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-3-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
hw/ppc/spapr_hcall.c diff | blob | history
target/ppc/cpu-qom.h diff | blob | history
target/ppc/cpu.h diff | blob | history
target/ppc/excp_helper.c diff | blob | history
target/ppc/translate.c diff | blob | history
target/ppc/translate_init.c.inc diff | blob | history
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