spi: bcm63xx-hsspi: Fix multi-bit mode setting
authorWilliam Zhang <william.zhang@broadcom.com>
Thu, 9 Feb 2023 20:02:41 +0000 (12:02 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 10 Mar 2023 08:39:30 +0000 (09:39 +0100)
commit528181646644c68862721d54c47d77dc7e396fb4
tree353938a0196fdad623e732b015d0eb8f0b454184
parentcaed289f95f26148e9e476cd677d1613cbddbc6a
spi: bcm63xx-hsspi: Fix multi-bit mode setting

[ Upstream commit 811ff802aaf878ebbbaeac0307a0164fa21e7d40 ]

Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.

This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.

Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver")
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/spi/spi-bcm63xx-hsspi.c