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target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
authorAlex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Mon, 30 Nov 2020 17:01:17 +0000 (17:01 +0000)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 18 Dec 2020 05:56:43 +0000 (21:56 -0800)
commit529577457cbba9e429af629c46204f63e50fa832
tree0b64abe8cb934d740a544d8ae3735d6c17a1b950tree | snapshot
parentc63ca4ff7f81116c26984973052991ff0bd7caeccommit | diff
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR

The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).

Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h diff | blob | history
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