clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate
authorFrank Oltmanns <frank@oltmanns.dev>
Sun, 10 Mar 2024 13:21:14 +0000 (14:21 +0100)
committerJernej Skrabec <jernej.skrabec@gmail.com>
Mon, 15 Apr 2024 21:23:21 +0000 (23:23 +0200)
commit52b1429e0c51a4ebbdf573ad97c7fb6d34f011a2
tree9ad06ee16ec849faf21c3e8b8ff08b8abb40763b
parent5723879c145255d2502a3f8f3a21a16332b24366
clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate

The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
 - M/N <= 3
 - (PLL_VIDEO0)/M >= 24MHz

Use these constraints.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-4-46fc80c83637@oltmanns.dev
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
drivers/clk/sunxi-ng/ccu-sun50i-a64.c