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(parent: d3d6def) | patch
hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1
authorJamin Lin <jamin_lin@aspeedtech.com>
Tue, 29 Oct 2024 09:17:27 +0000 (17:17 +0800)
committerCédric Le Goater <clg@redhat.com>
Mon, 4 Nov 2024 10:33:13 +0000 (11:33 +0100)
commit53b316926969d55646b5d6dd8f49e74e440a44f1
tree52ed41e81d31e4982abda40e81031c3915894291tree | snapshot
parentd3d6def468ff18b387ced3de79c0339aa7c1c78dcommit | diff
hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1

The size of SDHCI capabilities register is 64bits, so introduces new
Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244).

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[ clg: Fixed code alignment ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
hw/sd/aspeed_sdhci.c diff | blob | history
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