target/riscv: support for 128-bit bitwise instructions
authorFrédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Thu, 6 Jan 2022 21:01:00 +0000 (22:01 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 8 Jan 2022 05:46:10 +0000 (15:46 +1000)
commit568f247f69f9297a7a8816f46ce74a265a96ca8d
treef3667184c276a2ad2ff17d3602161130d65a032d
parenta2f827ff4f4486b8aa8fce180452463ec2b62f53
target/riscv: support for 128-bit bitwise instructions

The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-11-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/translate.c