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(parent: 2852bfb) | patch
clk: sunxi-ng: h6: fix PWM gate/reset offset
authorRongyi Chen <chenyi@tt-cool.com>
Fri, 10 Aug 2018 15:16:38 +0000 (23:16 +0800)
committerChen-Yu Tsai <wens@csie.org>
Mon, 27 Aug 2018 02:35:04 +0000 (10:35 +0800)
commit58c0f79887d5e425fe6a9fd542778e50df69e9c6
tree6de7e85a2f62c31958b4f130647a5d84fc230200tree | snapshot
parent2852bfbf4f168fec27049ad9ed20941fc9e84b95commit | diff
clk: sunxi-ng: h6: fix PWM gate/reset offset

Currently the register offset of the PWM bus gate in Allwinner H6 clock
driver is wrong.

Fix this issue.

Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Rongyi Chen <chenyi@tt-cool.com>
[Icenowy: refactor commit message]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
drivers/clk/sunxi-ng/ccu-sun50i-h6.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git