target/mips: Add emulation of MXU instructions for 32-bit load/store
authorSiarhei Volkau <lis8215@gmail.com>
Thu, 8 Jun 2023 10:41:50 +0000 (13:41 +0300)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 10 Jul 2023 21:33:38 +0000 (23:33 +0200)
commit59db94656d21e17a365af2e3b8f7e66b60e22810
tree44430a908eae15c459e23e86df7df484cb3c02f0
parent99eff13120c8695f5d14b2edfe24739dd13b982f
target/mips: Add emulation of MXU instructions for 32-bit load/store

Add support for emulating:
- S32LDDV and S32LDDVR
- S32STD and S32STDR
- S32STDV and S32STDVR
MXU instructions.

Add support for emulating MXU instructions with address register
post-modify counterparts:
- S32LDI and S32LDIR
- S32LDIV and S32LDIVR
- S32SDI and S32SDIR
- S32SDIV and S32SDIVR

Refactor support for emulating the S32LDD and S32LDDR instructions.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-2-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips/tcg/mxu_translate.c