target/riscv: Fix the hpmevent mask
authorAtish Patra <atishp@rivosinc.com>
Thu, 6 Feb 2025 09:58:46 +0000 (01:58 -0800)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 4 Mar 2025 05:42:54 +0000 (15:42 +1000)
commit59eaf1570456b701fe6dfa4a8f747e65633c385f
tree1f525b57a9a95c01c8498a2c6b4842f20c0674af
parent81819038d7d01c6c8c12005b5904356efc09a909
target/riscv: Fix the hpmevent mask

As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.

[1]https://github.com/riscv/riscv-isa-manual/issues/1578

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250206-pmu_minor_fixes-v2-1-1bb0f4aeb8b4@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h