clk: qcom: Add A7 PLL support
authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Mon, 18 Jan 2021 04:11:55 +0000 (09:41 +0530)
committerStephen Boyd <sboyd@kernel.org>
Mon, 8 Feb 2021 17:46:23 +0000 (09:46 -0800)
commit5a5223ffd7ef721b59be38e2ce83e0a73dbb8942
tree0ed78566736e4746cbbf53e3ac1e6e4aa5a68cc6
parentee778e069dd49cf476f3939d62f31346cf730080
clk: qcom: Add A7 PLL support

Add support for PLL found in Qualcomm SDX55 platforms which is used to
provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
frequency clock to the CPU above 1GHz as compared to the other sources
like GPLL0.

In this driver, the power domain is attached to the cpudev. This is
required for CPUFreq functionality and there seems to be no better place
to do other than this driver (no dedicated CPUFreq driver).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210118041156.50016-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/qcom/Kconfig
drivers/clk/qcom/Makefile
drivers/clk/qcom/a7-pll.c [new file with mode: 0644]