drm/i915: Give CPU transcoder timing registers TRANS_ prefix
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 13 Feb 2023 22:52:49 +0000 (00:52 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 17 Feb 2023 21:21:32 +0000 (23:21 +0200)
commit5ac421a9ec6668369b7910d4b1e7f5e7e9e9ec94
tree6c7b49f291c759f1c882009c24eaea8a9035e137
parent48630a3151b0373f005270c69f0caaaf08e22fd3
drm/i915: Give CPU transcoder timing registers TRANS_ prefix

Name the CPU transcoder timing registers TRANS_FOO rather than
just FOO. This is the modern name, after the pipe/transcoder split
happened. Makes it a bit more obvious whether you pass in a pipe or
a transcoder.

PIPESRC is a bit special as it's a pipe register, even though it
lives in the transcoder registers range (0x60000 instead of 0x70000).

And BCLRPAT I suppose is a transcoder register (since it has something
to do with the timing generator), but it doesn't even exist after gen4
so I left it to use the only name it ever had in bspec.

And while at it let's pass in the correct enum in few more
places why don't we. Although in all those places the distinction
doesn't matter.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/icl_dsi.c
drivers/gpu/drm/i915/display/intel_crt.c
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_pch_display.c
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/gvt/handlers.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_gvt_mmio_table.c