target: riscv: Add Svvptc extension support
authorAlexandre Ghiti <alexghiti@rivosinc.com>
Wed, 28 Aug 2024 08:36:51 +0000 (10:36 +0200)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 2 Oct 2024 05:11:51 +0000 (15:11 +1000)
commit5b8764193be027b2298133a819358f636ff53962
tree51b67544c25446961b7c3d1c360b023bac68d5d4
parent55c136599f512a86e3fec9f77b6b5a30a6b34cca
target: riscv: Add Svvptc extension support

The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.

Since qemu already exposes Svvptc behaviour, let's enable it by default
since it allows to drastically reduce the number of sfence.vma emitted
by S-mode.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240828083651.203861-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h