RISC-V: KVM: Add support for SBI extension registers
authorAndrew Jones <ajones@ventanamicro.com>
Wed, 20 Dec 2023 16:00:20 +0000 (17:00 +0100)
committerAnup Patel <anup@brainfault.org>
Sat, 30 Dec 2023 05:56:33 +0000 (11:26 +0530)
commit5b9e41321ba919dd051c68d2a1d2c753aa61634c
treeea69aa9b76c394466a1fd6b93aad99b74fed07a6
parent38b3390ee4880140b6245fe3273fe9ce53f65bde
RISC-V: KVM: Add support for SBI extension registers

Some SBI extensions have state that needs to be saved / restored
when migrating the VM. Provide a get/set-one-reg register type
for SBI extension registers. Each SBI extension that uses this type
will have its own subtype. There are currently no subtypes defined.
The next patch introduces the first one.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/kvm_vcpu_sbi.h
arch/riscv/include/uapi/asm/kvm.h
arch/riscv/kvm/vcpu_onereg.c
arch/riscv/kvm/vcpu_sbi.c