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(parent: ac81ff2) | patch
tests/tcg/xtensa: update test_fp0_conv for DFPU
authorMax Filippov <jcmvbkbc@gmail.com>
Tue, 30 Jun 2020 21:52:25 +0000 (14:52 -0700)
committerMax Filippov <jcmvbkbc@gmail.com>
Fri, 21 Aug 2020 19:48:16 +0000 (12:48 -0700)
commit5c10f488ea42dcdd63c8b37792c1e04d69208197
tree9e37129ee96a3db4824059e1fe5c3902669142cdtree | snapshot
parentac81ff227d264b29b8b75068a75d047e2d736d6fcommit | diff
tests/tcg/xtensa: update test_fp0_conv for DFPU

DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
tests/tcg/xtensa/test_fp0_conv.S diff | blob | history
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