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arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores
authorDuy Nguyen <duy.nguyen.rh@renesas.com>
Thu, 1 Feb 2024 14:19:17 +0000 (15:19 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 22 Feb 2024 10:03:32 +0000 (11:03 +0100)
commit5db13ece46d6948d5c26429c2827a78ed3a5afc5
treee6c6a1b644b18870075514e2dd6e3ae6b9eaed99tree | snapshot
parent20a942d60b34719df8a145e0364e90981380aefbcommit | diff
arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores

Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU
topology and PSCI support for enabling CPU cores.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c2a38a0da74915bf2a9171e53886c83a1c732934.1706796979.git.geert+renesas@glider.be
arch/arm64/boot/dts/renesas/r8a779h0.dtsi diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git