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(parent: 49735f7) | patch
target/mips: Add CP0 PWBase register
authorYongbok Kim <yongbok.kim@mips.com>
Tue, 9 Oct 2018 16:05:51 +0000 (18:05 +0200)
committerAleksandar Markovic <amarkovic@wavecomp.com>
Thu, 18 Oct 2018 18:37:20 +0000 (20:37 +0200)
commit5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6
treeaec770ca83d1d53eccd57353bf6b5e5eadea272atree | snapshot
parent49735f76db25bf10f57973d5249f17151b801760commit | diff
target/mips: Add CP0 PWBase register

Add PWBase register (CP0 Register 5, Select 5).

The PWBase register contains the Page Table Base virtual address.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
target/mips/cpu.h diff | blob | history
target/mips/machine.c diff | blob | history
target/mips/translate.c diff | blob | history
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