drm/amd/display: Enable DCN clock gating for DCN35
authorDaniel Miess <daniel.miess@amd.com>
Thu, 12 Oct 2023 16:55:47 +0000 (12:55 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 17 Nov 2023 14:30:50 +0000 (09:30 -0500)
commit5f70d4ff8095a2ad362d2a00eb8d9f7e20f3daa1
treee48451c935e8802f2b0f55ed8858ff17de71a7ab
parent673d6d73eba79a1205ac403b68ef63da1c823da2
drm/amd/display: Enable DCN clock gating for DCN35

[WHY & HOW]
Enable DCN clock gating for DCN35.
Disable DTBCLK gate before link training
and re-enable afterwards

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h