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(parent: 7c51048) | patch
target-arm: A64: Add SIMD ZIP/UZP/TRN
authorMichael Matz <matz@suse.de>
Fri, 31 Jan 2014 14:47:31 +0000 (14:47 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 31 Jan 2014 14:47:31 +0000 (14:47 +0000)
commit5fa5469c08f6e51eed26d6d54e0be8682723d3df
tree96dd7b74679afa9dd0625e1b216219f60be49b8atree | snapshot
parent7c51048fa918f64806adf0f76166e9940d772eb1commit | diff
target-arm: A64: Add SIMD ZIP/UZP/TRN

Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: use new do_vec_get/set etc functions and generally update to new
 codebase standards; refactor to pull per-element loop outside switch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm/translate-a64.c diff | blob | history
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