target/riscv: Move Zhinx* extensions on ISA string
authorTsukasa OI <research_trasio@irq.a4lg.com>
Tue, 10 May 2022 11:29:07 +0000 (20:29 +0900)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 23 May 2022 23:48:20 +0000 (09:48 +1000)
commit6047dcc2459fc6d1c49c4aa02e2e902dd3113856
treecce12f5ae6302267dec57027d578a1fa394d43a0
parent77046729f943ce2055648e8339ddd688dd67dd83
target/riscv: Move Zhinx* extensions on ISA string

This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
Because extension category ordering of "H" is going to be after "V",
their ordering is going to be valid (on canonical order).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c