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(parent: d6f20da) | patch
target/riscv: Use the RISCVException enum for CSR operations
authorAlistair Francis <alistair.francis@wdc.com>
Thu, 1 Apr 2021 15:17:57 +0000 (11:17 -0400)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 11 May 2021 10:02:06 +0000 (20:02 +1000)
commit605def6eeee5e4b6293963aa86be6e637e48bfb3
treec17daba427c4ef6341109eeb2f3acd7515496afftree | snapshot
parentd6f20dacea5147a9136ec3ecc7124440c16ba862commit | diff
target/riscv: Use the RISCVException enum for CSR operations

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
target/riscv/cpu.h diff | blob | history
target/riscv/csr.c diff | blob | history
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