dt-bindings: pinctrl: renesas: Document RZ/G3S SoC
authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Fri, 29 Sep 2023 05:39:07 +0000 (08:39 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 13 Oct 2023 07:38:05 +0000 (09:38 +0200)
commit60e4dc192ce2ebabcdd7c3487387a802110dc1a5
tree08f7706f3c3b3ed4b00506062d226a3103239842
parentae5b425faf1074a757fad093085f6be654b7db99
dt-bindings: pinctrl: renesas: Document RZ/G3S SoC

Add documentation for the pin controller found on the Renesas RZ/G3S
(R9A08G045) SoC.  Compared to RZ/G2{L,UL}, RZ/G3S has 82 general-purpose
IOs, no slew rate and output impedance support, and more values for
drive strength which needs to be expressed in microamp.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-21-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml