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target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions
authorSiarhei Volkau <lis8215@gmail.com>
Thu, 8 Jun 2023 10:42:07 +0000 (13:42 +0300)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 10 Jul 2023 21:33:38 +0000 (23:33 +0200)
commit6191a807fb865804c08b60b06393f25673f2fb64
treea9b48f09d49fd944381f9156ed2fc40a5c4c3900tree | snapshot
parent513cfdae7a45a705f2fb2919ad95c82f66169c6ecommit | diff
target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions

These instructions are all dual 16-bit addition/subtraction in
various combinations. The instructions are grouped in pool13,
see the opcode organization in the file.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-19-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips/tcg/mxu_translate.c diff | blob | history
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