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(parent: 4aef519) | patch
target/riscv: Fix wrong expanding for c.fswsp
authorKito Cheng <kito.cheng@gmail.com>
Tue, 26 Mar 2019 09:27:17 +0000 (17:27 +0800)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 26 Mar 2019 10:17:30 +0000 (03:17 -0700)
commit620455350a8da7cc62ae82cb69dd5c556f744136
treed6fa9ea50e3a9e1d2361869b8273881fdfdaa9dftree | snapshot
parent4aef51963924fd58ffe88daebbe8055a360d7c10commit | diff
target/riscv: Fix wrong expanding for c.fswsp

base register is no rs1 not rs2 for fsw.

Signed-off-by: Kito Cheng <kito.cheng@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/insn_trans/trans_rvc.inc.c diff | blob | history
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