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MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs
authorFelix Fietkau <nbd@nbd.name>
Mon, 16 May 2016 17:51:54 +0000 (19:51 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 17 May 2016 09:12:38 +0000 (11:12 +0200)
commit6241bf6a59a41c7ca742c043416b6d57109c6b5d
treebb03d4a5c0d9d2fb30bcb8cbd6fe13fe237b2643tree | snapshot
parentbad50d79255a8a479ea63bea89e859bf08fd0f24commit | diff
MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs

AR913x, AR724x and AR933x are the only SoCs where the
ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
Invert the logic to make the code compatible with AR95xx

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Cc: albeu@free.fr
Cc: sergei.shtylyov@cogentembedded.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13257/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/ath79/common.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git