clk: renesas: r9a09g011: Add CSI related clocks
authorFabrizio Castro <fabrizio.castro.jz@renesas.com>
Thu, 22 Jun 2023 11:33:38 +0000 (12:33 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 10 Jul 2023 07:31:53 +0000 (09:31 +0200)
commit63370298426b850220bba40012fb801a48c5fd14
treee5a3a047aaeaaebbe0425adad844f82916bc6ff5
parentadf6b916c9ee65503d4e7b9650a66e65f5064c3f
clk: renesas: r9a09g011: Add CSI related clocks

The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2
CSI3, CSI4, and CSI5), however Linux is only allowed control
of CSI0 and CSI4.
CSI0 shares its reset and PCLK lines with CSI1, CSI2, and CSI3.
CSI4 shares its reset and PCLK lines with CSI5.

This commit adds support for the relevant clocks.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230622113341.657842-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g011-cpg.c