openrisc: Support storing and restoring fpu state
authorStafford Horne <shorne@gmail.com>
Fri, 14 Apr 2023 07:25:58 +0000 (08:25 +0100)
committerStafford Horne <shorne@gmail.com>
Wed, 26 Apr 2023 14:08:06 +0000 (15:08 +0100)
commit63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf
treeb547d7264d6e02178c8e755168edb0d17702f760
parent812489ac4dd91144a74ce65ecf232252a2e406fb
openrisc: Support storing and restoring fpu state

OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions.  We need to save
only the floating point status and control register, FPCSR.

Add support to maintain the FPCSR unconditionally upon exceptions and
switches.  On machines that do not support FPU this will always just
store 0x0 and restore is a no-op.  On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).

Signed-off-by: Stafford Horne <shorne@gmail.com>
arch/openrisc/include/asm/ptrace.h
arch/openrisc/kernel/entry.S
arch/openrisc/kernel/traps.c