target/riscv: remove MISA properties from isa_edata_arr[]
authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Thu, 6 Apr 2023 18:03:33 +0000 (15:03 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 5 May 2023 00:49:50 +0000 (10:49 +1000)
commit6508272a8a92c46f0c1161466bc607ea6aea302d
tree7ba1e8d701988847d169fd29d2fadeedff48be0d
parent1ffa805c9d07bf1059d11a183540a3f07d02ea11
target/riscv: remove MISA properties from isa_edata_arr[]

The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.

We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related verifications in a new function, removing it from
isa_edata_arr[].

We're also erroring it out instead of disabling, making the cpu_init()
function responsible for running an adequate priv spec for the MISA
extensions it wants to use.

Note that the RVV verification is being ignored since we're always have
at least PRIV_VERSION_1_10_0.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c