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target/riscv: Typo fix in sstc() predicate
authorAnup Patel <apatel@ventanamicro.com>
Tue, 8 Nov 2022 12:56:59 +0000 (18:26 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 6 Jan 2023 00:42:55 +0000 (10:42 +1000)
commit6535a443345d659882444f0db1fafd22ba1f803a
tree97974901476d3fb8db6ed0171f3066e978019071tree | snapshot
parent0a9a6cba8b9cad8786670fd8c9fa1b0d39bd00e8commit | diff
target/riscv: Typo fix in sstc() predicate

We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/csr.c diff | blob | history
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