RISC-V Physical Memory Protection
authorMichael Clark <mjc@sifive.com>
Fri, 2 Mar 2018 12:31:11 +0000 (01:31 +1300)
committerMichael Clark <mjc@sifive.com>
Tue, 6 Mar 2018 19:30:28 +0000 (08:30 +1300)
commit65c5b75c38b3e56650fc63674039108697096f75
treeefc7daab35de8ad572ee08cca112c454f346e025
parent55c2a12cbcd3d417de39ee82dfe1d26b22a07116
RISC-V Physical Memory Protection

Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.

PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
The SiFive verification team have PMP test cases that will be run.

Nothing currently depends on PMP support. It would be preferable to keep
the code in-tree for folk that are interested in RISC-V PMP support.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daire McNamara <daire.mcnamara@emdalo.com>
Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
target/riscv/pmp.c [new file with mode: 0644]
target/riscv/pmp.h [new file with mode: 0644]