clk: agilex/stratix10: fix bypass representation
authorDinh Nguyen <dinguyen@kernel.org>
Fri, 11 Jun 2021 02:51:59 +0000 (21:51 -0500)
committerStephen Boyd <sboyd@kernel.org>
Sun, 27 Jun 2021 23:39:59 +0000 (16:39 -0700)
commit6855ee839699bdabb4b16cf942557fd763bcb1fa
tree328cecc21b4a9d285eab8073c924b725d64a025b
parentefbe21df3e889c0f4bf682c2b7e2465d60b0127c
clk: agilex/stratix10: fix bypass representation

Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp,
emac0/1/2) have a bypass setting that can use the boot_clk. The
previous representation was not correct.

Fix the representation.

Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/socfpga/clk-agilex.c
drivers/clk/socfpga/clk-s10.c