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(parent: 48794cd) | patch
clk: rockchip: rk3568: Add PLL rate for 126.4MHz
authorChris Morgan <macromorgan@hotmail.com>
Mon, 4 Dec 2023 18:57:17 +0000 (12:57 -0600)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 5 Dec 2023 09:43:42 +0000 (10:43 +0100)
commit685da6972647b486980c0cc8fd6bb5d3863fd6b7
treee99753bff348eb1fb1c969c5ecbf47ffe9eb933ftree | snapshot
parent48794cd57a67246acc53a3edfdececdbb5b98453commit | diff
clk: rockchip: rk3568: Add PLL rate for 126.4MHz

Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel
can run at a requested 60hz.

I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3568.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git