net: axienet: increase default TX ring size to 128
authorRobert Hancock <robert.hancock@calian.com>
Tue, 18 Jan 2022 21:41:32 +0000 (15:41 -0600)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 27 Jan 2022 10:05:33 +0000 (11:05 +0100)
commit6ad2daa516deafc6d6527d7f6450499340cf4064
tree62f7a6427f2d26d0a335eb822791024aa573376e
parent4928dd5990ea0ec8c9ffdb66663303862aca33c7
net: axienet: increase default TX ring size to 128

commit 2d19c3fd80178160dd505ccd7fed1643831227a5 upstream.

With previous changes to make the driver handle the TX ring size more
correctly, the default TX ring size of 64 appears to significantly
bottleneck TX performance to around 600 Mbps on a 1 Gbps link on ZynqMP.
Increasing this to 128 seems to bring performance up to near line rate and
shouldn't cause excess bufferbloat (this driver doesn't yet support modern
byte-based queue management).

Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/net/ethernet/xilinx/xilinx_axienet_main.c