mlxsw: reg: Add to SFMR register the fields related to CFF flood mode
authorPetr Machata <petrm@nvidia.com>
Mon, 20 Nov 2023 18:25:25 +0000 (19:25 +0100)
committerJakub Kicinski <kuba@kernel.org>
Tue, 21 Nov 2023 22:53:08 +0000 (14:53 -0800)
commit6b10371c386c381651e2ea42ae11be6c35004b55
treee2fe1bc1a18b758e567eb2529aa385370823c5ba
parent446bc1e9dec63b419751b8bdecba06fee631672e
mlxsw: reg: Add to SFMR register the fields related to CFF flood mode

Add the field cff_mid_base, which specifies at which point in PGT the
per-FID flood table is stored. Add cff_prf_id, the profile ID, which
determines on which row of the flood table a flood vector can be found for
a given traffic type.

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/3ad7ae38cf6534bedcd876f16090d109a814b3e3.1700503644.git.petrm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/mellanox/mlxsw/reg.h