clk: renesas: r9a07g043: Add GPIO clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 2 Apr 2022 07:46:23 +0000 (08:46 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 13 Apr 2022 10:30:18 +0000 (12:30 +0200)
commit6c185664b3d481292c41fbfe66ea19c84cb0237a
tree7f0734e0e78d8e8793331c8fa56d1a18e9247a9a
parentc8b088224c25ef4f5270f9de6a3516181b63f38c
clk: renesas: r9a07g043: Add GPIO clock and reset entries

Add GPIO clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c