KVM: riscv: selftests: Add RISCV_SBI_EXT_REG
authorAndrew Jones <ajones@ventanamicro.com>
Wed, 13 Dec 2023 17:09:56 +0000 (18:09 +0100)
committerAnup Patel <anup@brainfault.org>
Fri, 29 Dec 2023 07:01:47 +0000 (12:31 +0530)
commit6ccf119a4cc886678099a3526f37db98b67024d7
tree3775c08b15df38cc0a51bfd8e8d6718487b238d4
parent23e1dc45022eb65529aa30b1851a8d21a639c8f5
KVM: riscv: selftests: Add RISCV_SBI_EXT_REG

While adding RISCV_SBI_EXT_REG(), acknowledge that some registers
have subtypes and extend __kvm_reg_id() to take a subtype field.
Then, update all macros to set the new field appropriately. The
general CSR macro gets renamed to include "GENERAL", but the other
macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
tools/testing/selftests/kvm/include/riscv/processor.h
tools/testing/selftests/kvm/lib/riscv/processor.c