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target/arm: Implement CLRM instruction
authorPeter Maydell <peter.maydell@linaro.org>
Thu, 19 Nov 2020 21:55:54 +0000 (21:55 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 10 Dec 2020 11:44:55 +0000 (11:44 +0000)
commit6e21a013fbdf54960a079dccc90772bb622e28e8
treefe61490dd29e358be206973eec13dd354c8ff792tree | snapshot
parent83ff3d6add965c9752324de11eac5687121ea826commit | diff
target/arm: Implement CLRM instruction

In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
the general-purpose registers and APSR.  Implement this.

The encoding is a subset of the LDMIA T2 encoding, using what would
be Rn=0b1111 (which UNDEFs for LDMIA).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-6-peter.maydell@linaro.org
target/arm/t32.decode diff | blob | history
target/arm/translate.c diff | blob | history
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