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RISC-V: Implement atomic mip/sip CSR updates
authorMichael Clark <mjc@sifive.com>
Fri, 4 Jan 2019 23:24:04 +0000 (23:24 +0000)
committerPalmer Dabbelt <palmer@sifive.com>
Wed, 9 Jan 2019 18:00:52 +0000 (10:00 -0800)
commit71877e29696b10b6cf69faa1009dd0ec3202741e
tree631189c62c23c6a3f9a4c331ee36a780066a6c81tree | snapshot
parentc7b951718815694284501ed01fec7acb8654db7bcommit | diff
RISC-V: Implement atomic mip/sip CSR updates

Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/csr.c diff | blob | history
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