drm/xe/mtl: Handle PAT_INDEX offset jump
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 24 Mar 2023 21:04:15 +0000 (14:04 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 19 Dec 2023 23:30:25 +0000 (18:30 -0500)
commit7321a713c6c952d66d5fae8e8478c904b61bb735
treef095c97a7ec3652115134cb7b02a30f901f18156
parentf16a3f6335e84c07de4b5dd263f0c26e3a3fa5a4
drm/xe/mtl: Handle PAT_INDEX offset jump

Starting with MTL, the number of entries in the PAT table increased to
16.  The register offset jumped between index 7 and index 8, so a slight
adjustment is needed to ensure the PAT_INDEX macros select the proper
offset for the upper half of the table.

Note that although there are 16 registers in the hardware, the driver is
currently only asked to program the first 5, and we leave the rest at
their hardware default values.  That means we don't actually touch the
upper half of the PAT table in the driver today and this patch won't
have any functional effect [yet].

Bspec: 44235
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-7-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_pat.c