target/riscv: add shvstvecd
authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Wed, 18 Dec 2024 11:40:23 +0000 (08:40 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:34 +0000 (09:44 +1000)
commit73afe5c2f930b0ca86f7e8a43d501aa1908924ed
tree7cceaf58af0cb5eee3e2200eeaf187691933ec6b
parente306fff7f83285a385c29927833b1633e51d431b
target/riscv: add shvstvecd

shvstvecd is defined in RVA22 as:

"vstvec.MODE must be capable of holding the value 0 (Direct).
When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any
valid four-byte-aligned address."

This is always true for TCG so let's claim support for it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241218114026.1652352-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
tests/data/acpi/riscv64/virt/RHCT