aspeed/soc: fix incorrect dram size for AST2700
authorJamin Lin <jamin_lin@aspeedtech.com>
Tue, 4 Jun 2024 05:44:36 +0000 (13:44 +0800)
committerCédric Le Goater <clg@redhat.com>
Sun, 16 Jun 2024 19:08:54 +0000 (21:08 +0200)
commit7436db1063bbfecc2e498a7d795613b33312d665
tree39f13288f77f2ef7cf09b4b85da9b05b233ea295
parent92707992103effc3e4f6f8a03da59e627acc1e34
aspeed/soc: fix incorrect dram size for AST2700

AST2700 dram size calculation is not back compatible AST2600.
According to the DDR capacity hardware behavior,
if users write the data to the address which is beyond the ram size,
it would write the data to the "address % ram_size".
For example:
a. sdram base address "0x4 00000000"
b. sdram size 1 GiB
The available address range is from "0x4 00000000" to "0x4 3FFFFFFF".
If users write 0x12345678 to address "0x5 00000000",
the value of DRAM address 0 (base address 0x4 00000000) will be 0x12345678.

Add aspeed_soc_ast2700_dram_init to calculate the dram size and add
memory I/O whose address range is from "max_ram_size - ram_size" to max_ram_size
and its read/write handler to emulate DDR capacity hardware behavior.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
hw/arm/aspeed_ast27x0.c
include/hw/arm/aspeed_soc.h