drm/msm/a6xx: Fix unknown speedbin case
authorKonrad Dybcio <konrad.dybcio@linaro.org>
Tue, 26 Sep 2023 18:24:36 +0000 (20:24 +0200)
committerRob Clark <robdclark@chromium.org>
Mon, 9 Oct 2023 18:22:05 +0000 (11:22 -0700)
commit75cb60d4f5f762b12643b67cbefefcf05ecfd7eb
tree272ed995f08e1e4ecc9c93206a1cb6e3f64e3ecf
parentbeb3542320479cd59a08273be0b19dfea0b36042
drm/msm/a6xx: Fix unknown speedbin case

When opp-supported-hw is present under an OPP node, but no form of
opp_set_supported_hw() has been called, that OPP is ignored by the API
and marked as unsupported.

Before Commit c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to
device table"), an unknown speedbin would result in marking all OPPs
as available, but it's better to avoid potentially overclocking the
silicon - the GMU will simply refuse to power up the chip.

Currently, the Adreno speedbin code does just that (AND returns an
invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0
(which is conveniently always bound to fuseval == 0).

Fixes: c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/559604/
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/adreno/a6xx_gpu.c