gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
authorSteven Lee <steven_lee@aspeedtech.com>
Tue, 14 Dec 2021 04:02:38 +0000 (12:02 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 11 Jan 2022 14:35:16 +0000 (15:35 +0100)
commit75d840c0f5d79b4d71ecb8743ad3e7f82dd206a7
tree50a6200d7ae530a200006ce4ad53a6dee0bee567
parent7601a265696c2132007dfd30009d1cc902f12cbf
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler

commit e5a7431f5a2d6dcff7d516ee9d178a3254b17b87 upstream.

Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpio/gpio-aspeed-sgpio.c