clk: renesas: r8a779f0: Add SDHI0 clock
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Fri, 3 Jun 2022 23:34:37 +0000 (01:34 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 13 Jun 2022 09:53:18 +0000 (11:53 +0200)
commit75fe45a000a70ea35e2071eb7f8b873648590982
tree51cd50c41ab168aa00116aa566f772664889518c
parent61a6737fcad8810258bdf1329f063b58ac27b230
clk: renesas: r8a779f0: Add SDHI0 clock

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a779f0-cpg-mssr.c