drm/i915/vdsc: Refactor dsc register field macro
authorSuraj Kandpal <suraj.kandpal@intel.com>
Mon, 28 Aug 2023 05:42:54 +0000 (11:12 +0530)
committerAnimesh Manna <animesh.manna@intel.com>
Tue, 5 Sep 2023 09:09:18 +0000 (14:39 +0530)
commit76342fce58a58e3c8326a870adfb6b435ecd9abb
treecdf9409b1cb12e4c7389f2a64fbe8d04b1ff9ed8
parent1bb2af547a4bc2e053b398573d8ec7c3bf5ce69e
drm/i915/vdsc: Refactor dsc register field macro

This patch refactors dsc register related macros that prepares
the values to be written in the register. The current bit shifting
looks bad and going forward will not serve our purpose to readout
dsc register field values the change was suggested by Jani Nikula.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
drivers/gpu/drm/i915/display/intel_vdsc_regs.h