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target/i386: add sha512, sm3, sm4 feature bits
authorPaolo Bonzini <pbonzini@redhat.com>
Wed, 3 Jul 2024 11:42:49 +0000 (13:42 +0200)
committerPaolo Bonzini <pbonzini@redhat.com>
Thu, 7 Nov 2024 15:54:01 +0000 (16:54 +0100)
commit78be258c0eeba3d5613c37888889e84f2ba9bd94
tree6ead0b7f082469df799467024026022ee7964481tree | snapshot
parenta1dacb66915eb7d08a0596cc97068a37c39930d3commit | diff
target/i386: add sha512, sm3, sm4 feature bits

SHA512, SM3, SM4 (CPUID[EAX=7,ECX=1).EAX bits 0 to 2) is supported by
Clearwater Forest processor, add it to QEMU as it does not need any
specific enablement.

See https://lore.kernel.org/kvm/20241105054825.870939-1-tao1.su@linux.intel.com/
for reference.

Reviewed-by: Tao Su <tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/i386/cpu.c diff | blob | history
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