target/riscv: access configuration through cfg_ptr in DisasContext
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Wed, 2 Feb 2022 00:52:45 +0000 (01:52 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:24:18 +0000 (12:24 +1000)
commit79bf3b51acb4a6245b500005859e8b1d1611302f
tree2869f86c4d05e849ff7a2d2090de04ad2f5350aa
parent3b91323e33d85150eb482458b1f1e2b08a59d8a2
target/riscv: access configuration through cfg_ptr in DisasContext

The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure.  This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu>
[ Changes by AF:
 - Fixup checkpatch failures
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/insn_trans/trans_rvv.c.inc
target/riscv/insn_trans/trans_rvzfh.c.inc
target/riscv/translate.c