drm/i915: Make most pre-skl primary plane registers unlocked
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 10 Feb 2022 06:24:02 +0000 (08:24 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 24 Feb 2022 15:51:51 +0000 (17:51 +0200)
commit7ad9993b2368f2a861f335184cd2bb1909f13827
treef3e9a71f42e05112933fd892d2f541cac250682d
parent0225a90981c83408e9606b52a65edee1c6891106
drm/i915: Make most pre-skl primary plane registers unlocked

Drop the locks around most primary plane register writes.
The lock isn't needed since each plane's register are neatly
contained on their own cachelines.

The one exception we have to make is DSPADDR/DSPSURF which is
(ab)used to also trigger FBC nukes on pre-snb (since the
hardware doesn't seem to have any dedicated mechanism to
trigger nukes). So we need to keep the lock around it to
protect against the rmw performed by the fbc code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220210062403.18690-5-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
drivers/gpu/drm/i915/display/i9xx_plane.c