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(parent: 7113d61) | patch
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
authorRebecca Cran <rebecca@nuviainc.com>
Wed, 12 May 2021 18:23:37 +0000 (12:23 -0600)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 25 May 2021 15:01:43 +0000 (16:01 +0100)
commit7b9171cc83f37d078ae7d544d2bacd6a851453d8
treeb5fd0b66a46d39a9147f45ef859e2fb22d6ae035tree | snapshot
parent7113d618505b1ba7a0b029df2d2617a0d0259e37commit | diff
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210512182337.18563-4-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/cpu64.c diff | blob | history
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