KVM: arm64: nvhe: Synchronise with page table walker on TLBI
authorMarc Zyngier <maz@kernel.org>
Sat, 8 Apr 2023 16:04:24 +0000 (17:04 +0100)
committerMarc Zyngier <maz@kernel.org>
Fri, 14 Apr 2023 07:23:29 +0000 (08:23 +0100)
commit7e1b2329c205d0a08ebaf3f619318a8a18f36644
tree860df5432dc2520a90b1f67ede76560dcbb370fe
parent55b5bac15939dec3cbcbee1f6271bc3a4afd4534
KVM: arm64: nvhe: Synchronise with page table walker on TLBI

A TLBI from EL2 impacting EL1 involves messing with the EL1&0
translation regime, and the page table walker may still be
performing speculative walks.

Piggyback on the existing DSBs to always have a DSB ISH that
will synchronise all load/store operations that the PTW may
still have.

Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
arch/arm64/kvm/hyp/nvhe/tlb.c