drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA
authorImre Deak <imre.deak@intel.com>
Mon, 29 Jan 2024 17:55:32 +0000 (19:55 +0200)
committerImre Deak <imre.deak@intel.com>
Wed, 10 Apr 2024 16:27:23 +0000 (19:27 +0300)
commit7e3025c6e7bd067d0a6be8e102b6182a04f5c5d6
tree63002bb5eca10e070ea44fee16d4117d9a12a354
parent377cc98b451d049bf3d965fb414d9210a0e5959f
drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA

Disable the workaround inserting an SF symbol between the last DSC EOC
symbol and the subsequent BS symbol. The WA is enabled by default -
based on the register's reset value - and Bspec requires disabling it
explicitly. Bspec doesn't provide an actual WA ID for this.

Bspec: 50054, 65448, 68849

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-6-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/i915_reg.h